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SVA sequence and/or #943

Merged
merged 1 commit into from
Jan 22, 2025
Merged

SVA sequence and/or #943

merged 1 commit into from
Jan 22, 2025

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kroening
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The 1800-2017 SystemVerilog grammar allows a and b and a or b to be either a sequence, or a property. If both a and b are sequences, then a and b and a or b is a sequence as well.

This changes the grammar to allow the sequence case.

@kroening kroening marked this pull request as ready for review January 21, 2025 19:00
The 1800-2017 SystemVerilog grammar allows "a and b" and "a or b" to be
either a sequence, or a property.  If both "a" and "b" are sequences, then
"a and b" and "a or b" is a sequence as well.

This changes the grammar to allow the sequence case.
@tautschnig tautschnig merged commit d923a32 into main Jan 22, 2025
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@tautschnig tautschnig deleted the sequence_and_or branch January 22, 2025 16:33
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